This invention relates to programmable logic device integrated circuits, and more particularly, to testing programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools help the designer to implement the custom logic circuit using the resources available on a given programmable logic device. When the design process is complete, the CAD tools generate configuration data files. The configuration data is loaded into programmable logic devices to configure them to perform the desired custom logic function.
Programmable logic devices contain programmable memory elements. With one typical arrangement, a programmable logic device has an array of volatile memory elements based on random-access-memory (RAM). During device programming, memory elements in the array are loaded with configuration data. Memory elements that are loaded with configuration data in this way are sometimes referred to as configuration random-access-memory cells. Once loaded, each memory element produces a corresponding static output signal. The static output signals from the memory elements are applied to circuit components in the programmable logic.
The programmable logic generally uses complementary metal-oxide-semiconductor (CMOS) technology and includes components such as n-channel metal-oxide-semiconductor (NMOS) transistors and p-channel metal-oxide-semiconductor (PMOS) transistors. The states of the static output signals control the states of the transistors. In general, some of the static output signals produced by the memory elements will be high and some will be low. When, for example, a memory element applies a high output signal to the gate of an n-channel metal-oxide-semiconductor transistor, that transistor will be turned on. If a memory element applies a low output to the gate of the n-channel metal-oxide-semiconductor transistor, the transistor will be turned off. By configuring the programmable logic in this way, the configuration data in the programmable memory elements can be used to implement a logic designer's desired custom circuit design using the resources available on the programmable logic device.
Power consumption is a critical challenge for modern integrated circuits such as programmable logic device integrated circuits. Circuits with poor power efficiency place undesirable demands on system designers. Power supply capacity may need to be increased, thermal management issues may need to be addressed, and circuit designs may need to be altered to accommodate inefficient circuitry.
One way to improve power efficiency is to selectively body bias the NMOS and PMOS transistors on an integrated circuit. NMOS and PMOS transistors have four terminals—a drain, a source, a gate, and a body. The body terminal, which is sometimes referred to as the well or bulk terminal, can be biased to adjust transistor performance. For example, a positive bias voltage can be applied to the body of a PMOS transistor and a negative bias voltage can be applied to the body of an NMOS transistor. These bias voltages increase the effective threshold voltages of the transistors and thereby reduce their leakage currents. The reductions in leakage current that are achieved by applying these types of body bias voltages reduce power consumption, but can slow transistor switching speeds. It can therefore be advantageous to use different body bias voltages for different regions of a circuit. Portions of a device that require low power consumption can use one body bias level (i.e., a body bias level that increases transistor threshold voltages). Portions of the device that require maximum switching speed can use another body bias level (i.e., a body bias level that reduces transistor threshold voltages).
To provide different body bias voltages to various portions of an integrated circuit, a set of high and low body bias voltages may be distributed throughout the integrated circuit using power supply distribution paths. Power supply voltage selection switches may be used to select which body bias voltage is routed to each portion of the integrated circuit. In a programmable logic device, power supply selection switches may be controlled by associated memory elements. During device programming, configuration data is loaded into the memory elements that configures the power supply voltage selection switches. This allows portions of the device that require high performance to be provided with body bias voltages that enhance transistor switching speed, while those portions of the device that do not require high performance can be operated with body bias voltages that reduce power consumption.
Power consumption efficiency may also be improved by appropriate selection of other power supply voltages. For example, a device may be powered using a low power supply level (e.g., 1.1 volts or less) for much of its core logic. Lowering the core logic supply in this way will reduce power consumption. However, logic circuits that are powered in this way may not perform as well as desired. For example, NMOS pass transistors may not turn on as fully as would be desired if they are only powered using 1.1 volt logic signals. In this type of environment, it can be beneficial to selectively use elevated power supply voltages. Such elevated power supply voltage may, for example, be used for at least some of the memory elements on a device.
The power supply voltages used for powering the memory elements on a programmable logic device control the range of the static output signals produced by the memory elements when loaded with configuration data. For example, if a memory element is powered using a positive power supply voltage of 1.1 volts and is loaded with a configuration bit that has a logic one value, the memory element will produce an output signal at 1.1 volts. By using an elevated memory element power supply level, the output of a memory element containing a logic can be raised to an elevated level such as 1.6 volts. The elevated 1.6 volt signal level will turn on the NMOS pass transistor more fully than a 1.1 volt signal level and will thereby improve device performance.
In order to provide a logic designer with the ability to adjust power supply levels, a programmable logic device may be provided with multilevel power supply distribution paths. Such paths can distribute multiple power supply voltages to various portions of a device. For example, positive power supply levels such as 1.1 volts and 1.6 volts may be distributed over the power supply distribution paths and ground power supply levels of 0 volts and −1 volts may be distributed over the power supply distribution paths. Programmable power supply selection switches may be used to selectively tap into desired power supply voltages at various portions on a device.
Programmable power supply selection switches may be controlled by associated memory elements. By loading appropriate configuration data into the memory elements, a logic designer can configure some regions of an integrated circuit to use one set of power supply levels and other regions of the integrated circuit to use another set of power supply levels. By adjusting the power supply levels that are used, performance and power consumption tradeoffs can be made with a high level of granularity, thereby optimizing device performance.
Programmable logic devices are tested during manufacturing. Because improper selection of a power supply voltage with a power supply selection switch may cause a circuit design to perform inadequately, it would be desirable to be able to provide a way in which to test whether power supply selection switches on an integrated circuit are functioning properly.